XAPP1064的仿真数据较慢输出就会切换

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以下为原文

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嗨umamahe，
我还没有尝试过实际的芯片，只是模拟。
但是，我会使用自定义板。
我担心的是路由后模拟，因为它表明输出没有像我在第一篇文章中所描述的那样切换。
谢谢。



以下为原文

Hi umamahe,
 
I have not tried it out on actual silicon yet, just simulation. I will, however, be using a custom board.
My concern is regarding post-route simulation as it indicates outputs are not switching as described in my first post.
 
Thanks.

MODS的，
这个问题没有解决。
不确定它是如何标记解决的。
谢谢



以下为原文

Mods,
 
This issue is not solved. Not sure how it was marked solved.
 
Thanks

alrodrig写道：
嗨，
我有一个类似于以下问题的问题：//forums.xilinx.com/t5/New-Users-Forum/serialization-using-spartan-6-oserdes/m-p/259034/highlight/true#M1566。
我试图以7：1的比例序列化并使用XAPP1064中显示的示例图15。
我的时钟是100Mhz所以数据将是700Mbps。
行为模拟工作正常。
问题
当我做路径后模拟时......如果数据模式类似于1010101，则在700Mbps时输出不会切换。如果数据较慢，如1100011，输出会切换。如果我将数据速率降低到520Mbps，则发布
无论数据模式如何，-route模拟都能正常工作。
我正在使用ISE14.7和斯巴达6 LX16 -2速度等级。
我距离制作电路板几个月，从未做过类似的设计。
如果其他人已经看到这个问题，那我正在讨论这个问题，只是模拟问题或“真正的”问题。没有错误或警告......我可以看到高速io时钟和serdestrobe。
我创建了一个非常简化的测试案例，只有一个LVDS通道和tbench。
要传输的数据可以在TB中更改。
谢谢你的帮助。
设计是否符合时序要求？
你的时间限制是否正确？
----------------------------是的，我这样做是为了谋生。



以下为原文

alrodrig wrote:
Hi,
 
I have an issue similar to the one here http://forums.xilinx.com/t5/New-Users-Forum/serialization-using-spartan-6-oserdes/m-p/259034/highlight/true#M1566.
 
 
I am trying to serialize with a 7:1 ratio and used the example shown in XAPP1064 Fig 15.

My clock is 100Mhz so the data will be 700Mbps. Behavioral simulation works fine. The problem
is when I do a post-route simulaiton... At 700Mbps the outputs will not switch if the data pattern is something like 1010101. The outputs do switch if data is slower such as 1100011. If I slow the data rate down to 520Mbps then post-route simulation works fine no matter the data pattern.
 
I am using ISE14.7 and spartan 6 LX16 -2 speed grade. I am months away from making a board and have never done a similar design.  I'm wodering if anyone else has seen this and wether it's a simulation issue only or a "real" problem. There are no errors or warnings... I can see the high speed io clock and the serdestrobe.
 
I have created a very stripped down test case with only one LVDS lane and tbench. The data to be transmitted can be changed in the TB.
 
Thanks for any help.

Does the design meet timing requirements? Are your timing constraints correct?
----------------------------Yes, I do this for a living.