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王欢

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[问答]

斯巴达6上升时间下降时间怎么减少

嗨,
我试图减少上升时间和下降时间,包括在spartan 6中IO引脚的过冲。
我没有应用约束
tr = 2.5ns
tf = 2.5ns
过冲= 11%
我应用了6mA的驱动约束.....为此我得到了新的结果
tr = 3.5ns
TF =为2.5ns
过冲= 2%
我期待着下降时间也有所改善.....是驱动所有关于当前的驱动......当前下沉的控制是什么?....
我应该应用回转约束而不是Drive constarint ......请建议.....

以上来自于谷歌翻译


以下为原文

Hi,
I was trying to reduce the rise time and falltime including overshoot for an IO pin out in spartan 6.

Without applying constraint I was getting
tr = 2.5ns
tf = 2.5ns
Overshoot = 11%

I applied a Drive constraint for 6mA.....for this i got new result
tr = 3.5ns
tf=2.5ns
Overshoot = 2%

I was expecting an improvement for fall time too..... is Drive all about current drive .... what contrls the current sink??....

Should I apply slew constraint instead of Drive constarint ......Please advice.....

回帖(3)

刘丰标

2019-4-10 13:37:52
您使用的I / O标准是什么?
如果使用LVTTL和LVCMOS输出,则可以相应地更改转换速率属性
SLEW属性的允许值为:•SLEW = SLOW(默认)•SLEW = FAST•SLEW = QUIETIOT在UCF文件中指定为约束时,SLEW属性使用以下语法:NET SLEW =“”;

以上来自于谷歌翻译


以下为原文

what is the I/O standard you are using?
 if you are using LVTTL and LVCMOS output then you can change the slew rate attribute accordingly
The allowed values for the SLEW attribute are:
• SLEW = SLOW (Default)
• SLEW = FAST
• SLEW = QUIETIO
The SLEW attribute uses the following syntax when specified as a constraint in the UCF
file:
NET SLEW = "";
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李欣

2019-4-10 13:57:17
我试过SLEW = QUIETIO ..
上升时间2.8ns
下降时间为2.5ns,超调超过10%......
我的目标是减少数字输出中的振铃....
我试过输出终止...
OUT_TERM = UNTUNED_75
在这里,我的上升时间为5.2ns,下降时间为3.5ns ....
为什么上升和下降时间是不对称的?....

以上来自于谷歌翻译


以下为原文

I tried SLEW = QUIETIO..
 
Rise time 2.8ns
Fall time 2.5ns and overshoot more than 10%...
 
My aim is to reduce the ringing in the digital output....
I tried output termination ...
OUT_TERM =  UNTUNED_75
here I was getting risetime 5.2ns and falltime as 3.5ns....
 
Why the rise and fall time is asymmetric??....
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潘晶燕

2019-4-10 14:10:23
R,
流程变化使事情变得不同。
驱动电流是保证的最小值。
它可能远远超过上拉和下拉(并且它们永远不会完全相等,一个可能比另一个强40%)。
使用IBIS建模工具(如Mentor的Hyperlinx或其他CAD SI工具)执行信号完整性分析。
甚至可以使用spice(一些spice版本支持IBIS模型)。
http://www.xilinx.com/products/technology/signal-integrity.html
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

r,
 
Process variations make things different.  The drive current is the guaranteed minimum.  It is likely much more than that for pull up, and pull down (and they are never exactly equal, and one could be 40% stronger than the other).
 
Perform a signal integrity analysis with an IBIS modeling tool, like Mentor's Hyperlinx, or another CAD SI tool.  One may even use spice (some spice versions support IBIS models).
 
http://www.xilinx.com/products/technology/signal-integrity.html
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose
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