你好，巴美，
1,2。32 K的外部LPO对于上电序列是非常需要的。不能删除用于空间限制的连接（数据表中的数字编号20.1.2）。
三。内部睡眠模式使用32 K时钟作为瞌睡模式中的参考时钟，无线电、模拟域和大多数线性稳压器断电。其余的CYW433W保持在一个空闲状态上电。所有的主时钟（PLL，晶体振荡器）被关闭，以将有功功率降低到最小值。32.768千赫LPO时钟仅适用于PMU定序器。
4、5。请浏览数据表的页码11，以了解更多关于深度睡眠的信息。如果你仍然有同样的问题，请回复我们。它不会在整个睡眠期间保持BLE连接。但是在一定间隔之后，它会醒来并检查主/从连接的状态，然后再次回到深度睡眠。
6。如果您检查了数据表的第18部分，您可以发现泄漏电流规范以及所有其他相关的功耗规范。
7。在BT I2S通信时，CYW433W不需要通过UART接口进行通信。
以上来自于百度翻译
以下为原文
Hello Bimal,
1,2. The external LPO of 32k is very much required for the power-up sequence. You can not remove that connection for space constraints (check figure number 20.1.2 in the datasheet).
3. Internal sleep modes use the 32k clock as reference clock like in doze mode, the radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW4343W remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer.
4,5. Please go through the page number 11 of the datasheet to understand more about deep sleep. If you are still having questions regarding the same, please get back to us. It will not retain the BLE connection during the entire sleep period. But after a certain interval, it will wake up and check the status of the connection with Master/Slave and goes back to deep sleep again.
6. If you check out the section 18 of the datasheet, you could find the leakage current specifications there along with all the other relevant power consumption specifications.
7. At the time of BT I2S communication, CYW4343W does not require communicating over UART interface.
你好，巴美，
1,2。32 K的外部LPO对于上电序列是非常需要的。不能删除用于空间限制的连接（数据表中的数字编号20.1.2）。
三。内部睡眠模式使用32 K时钟作为瞌睡模式中的参考时钟，无线电、模拟域和大多数线性稳压器断电。其余的CYW433W保持在一个空闲状态上电。所有的主时钟（PLL，晶体振荡器）被关闭，以将有功功率降低到最小值。32.768千赫LPO时钟仅适用于PMU定序器。
4、5。请浏览数据表的页码11，以了解更多关于深度睡眠的信息。如果你仍然有同样的问题，请回复我们。它不会在整个睡眠期间保持BLE连接。但是在一定间隔之后，它会醒来并检查主/从连接的状态，然后再次回到深度睡眠。
6。如果您检查了数据表的第18部分，您可以发现泄漏电流规范以及所有其他相关的功耗规范。
7。在BT I2S通信时，CYW433W不需要通过UART接口进行通信。
以上来自于百度翻译
以下为原文
Hello Bimal,
1,2. The external LPO of 32k is very much required for the power-up sequence. You can not remove that connection for space constraints (check figure number 20.1.2 in the datasheet).
3. Internal sleep modes use the 32k clock as reference clock like in doze mode, the radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW4343W remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer.
4,5. Please go through the page number 11 of the datasheet to understand more about deep sleep. If you are still having questions regarding the same, please get back to us. It will not retain the BLE connection during the entire sleep period. But after a certain interval, it will wake up and check the status of the connection with Master/Slave and goes back to deep sleep again.
6. If you check out the section 18 of the datasheet, you could find the leakage current specifications there along with all the other relevant power consumption specifications.
7. At the time of BT I2S communication, CYW4343W does not require communicating over UART interface.
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