L6474接地和布局有什么建议

L6474芯片提供三个接地引脚（PGND，AGND，DGND）以及内部连接到上述所有三个的导热垫（EPAD）。如果我正确理解芯片的框图（数据表，第7页），PGND和AGND在芯片内连接在一起。在评估板中，单个接地层用于PGND，AGND，DGND和EPAD。在我们的应用中，必须避免将嘈杂的模拟电流耦合到数字域以及电路板的I / O区域。拆分DGND和AGND以及使用光耦合器可能有意义但我们需要防止接地回路。例如由于芯片内部连接。你这方面有什么建议吗？

＃board-layout #grounding＃l6474



以下为原文




The L6474 chip provides three ground pins (PGND, AGND, DGND) as well as a thermal pad (EPAD) connected internally to all three of the above. If I understand the chip's block diagram correctly (datasheet, p. 7), PGND and AGND are tied together within the chip. In the eval board a single ground plane is used for PGND, AGND, DGND and EPAD. In our application it is necessary to avoid coupling of noisy analog currents to the digital domain as well as to the I/O area of the board. Splitting DGND and AGND and using optocouplers may make sense but we need to prevent ground loops. e.g. due to chip-internal connections. Are there any recommendations from your side on this issue?
  
#board-layout #grounding #l6474