嗨，C.H.Chen
假设您在FX3主从之间有32位接口。Slave的DMA缓冲区大小分别为1K字节和8个这样的缓冲区。
地址和数据计数器的目的是引入流量控制和防止数据丢失。
地址和数据计数器（它们仅仅是2个计数器和名称不重要）在主机上跟踪有多少字节的数据实际上已经写入奴隶。GPIF状态机中的每个DRMA数据将发送32位数据（4字节），然后地址和数据计数器递增1。当地址计数器达到256（256×4= 1K字节）时，这意味着从存储器中的缓冲器完全被填充。有一个延迟是从切换到下一个缓冲区。主机应该确保它在缓冲区切换期间不驱动数据（通常微秒）。WrdDATAYAWAL只是一个状态，ADDISSH计数器被重置为0，这需要足够的时间来确保从机切换到下一个缓冲器。
类似地，数据计数器加载2048（对于8K缓冲器，2048×4字节）。当数据计数器值命中时，您已经写入了从机中的所有8个缓冲器，返回到RDYWRSIDLE，将计数器重新装入0，并检查标志B（这说明Slave是否释放了任何缓冲器），并相应地驱动数据。
希望这有帮助
当做
穆达比尔卡比尔
以上来自于百度翻译
以下为原文
Hi C.H.Chen
Lets say you have 32 bit interface between FX3 Master and Slave. And Slave has DMA buffer size of 1K bytes each and 8 such buffers.
The purpose of address and data counter is to introduce flow control and prevent data loss,.
The Address and data counter ( They are just 2 counters and names dont matter) in master keeps track of how many bytes of data have actually been written to the Slave. Every DR_DATA in gpif state machine will send out 32 bits of data ( 4 bytes) and then Address and data counters are incremented by 1. When address counter reaches 256 ( 256 x4 = 1K bytes), It means that a buffer in Slave has been filled completely. There is a delay is Slave switching to next buffer. The master should ensure that it doesnt drive data during this buffer switching ( usually few microseconds). WR_DATA_WAIT is just a state where address_counter is reset to 0 and this takes enough time to ensure that the Slave has switch to next buffer.
Similarly data counter is loaded with 2048 ( for 8K buffer, 2048x4 bytes). When data counter value hits, you have written to all 8 buffers in slave, you go back to RD_WR_IDLE , reload the counter to 0 and check flag B ( which tells if Slave has any buffer freed or not) and accordingly drive data.
Hope this helps
Regards
Mudabir Kabir
嗨，C.H.Chen
假设您在FX3主从之间有32位接口。Slave的DMA缓冲区大小分别为1K字节和8个这样的缓冲区。
地址和数据计数器的目的是引入流量控制和防止数据丢失。
地址和数据计数器（它们仅仅是2个计数器和名称不重要）在主机上跟踪有多少字节的数据实际上已经写入奴隶。GPIF状态机中的每个DRMA数据将发送32位数据（4字节），然后地址和数据计数器递增1。当地址计数器达到256（256×4= 1K字节）时，这意味着从存储器中的缓冲器完全被填充。有一个延迟是从切换到下一个缓冲区。主机应该确保它在缓冲区切换期间不驱动数据（通常微秒）。WrdDATAYAWAL只是一个状态，ADDISSH计数器被重置为0，这需要足够的时间来确保从机切换到下一个缓冲器。
类似地，数据计数器加载2048（对于8K缓冲器，2048×4字节）。当数据计数器值命中时，您已经写入了从机中的所有8个缓冲器，返回到RDYWRSIDLE，将计数器重新装入0，并检查标志B（这说明Slave是否释放了任何缓冲器），并相应地驱动数据。
希望这有帮助
当做
穆达比尔卡比尔
以上来自于百度翻译
以下为原文
Hi C.H.Chen
Lets say you have 32 bit interface between FX3 Master and Slave. And Slave has DMA buffer size of 1K bytes each and 8 such buffers.
The purpose of address and data counter is to introduce flow control and prevent data loss,.
The Address and data counter ( They are just 2 counters and names dont matter) in master keeps track of how many bytes of data have actually been written to the Slave. Every DR_DATA in gpif state machine will send out 32 bits of data ( 4 bytes) and then Address and data counters are incremented by 1. When address counter reaches 256 ( 256 x4 = 1K bytes), It means that a buffer in Slave has been filled completely. There is a delay is Slave switching to next buffer. The master should ensure that it doesnt drive data during this buffer switching ( usually few microseconds). WR_DATA_WAIT is just a state where address_counter is reset to 0 and this takes enough time to ensure that the Slave has switch to next buffer.
Similarly data counter is loaded with 2048 ( for 8K buffer, 2048x4 bytes). When data counter value hits, you have written to all 8 buffers in slave, you go back to RD_WR_IDLE , reload the counter to 0 and check flag B ( which tells if Slave has any buffer freed or not) and accordingly drive data.
Hope this helps
Regards
Mudabir Kabir
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